A clock and data recovery method based on charge pump PLL was developed to archive medium data rate serial digital communication with simple line transceivers.The phase detector was realized by FPGA.A delay chain was constructed by delay elements with the same fixed delay.Every output of the delay elements was latched by the VCO output clock when the input signal went through the delay chain.The latched result was used to detect the data transition

which reflected the phase difference between the input signal and the VCO output clock.The VCO control voltage was adjust by charge pump to reduce the phase difference and archive phase lock.The loop filter was a passive filter

parameters of which were calculated from parameters of the delay chain and VCO.The experimental result shows that the clock of a 64Mbps transmission was recovered with a jitter less than 200 ps.