Control of field flatness based on FPGA for multi-cell cavity

Zhigang ZHANG; Yubin ZHAO; Kai XU; Xiang ZHENG; Zheng LI; Shenjie ZHAO; Qiang CHANG; Hongtao HOU; Jianfei LIU

doi:10.11889/j.0253-3219.2017.hjs.40.020101

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Control of field flatness based on FPGA for multi-cell cavity

SYNCHROTRON RADIATION TECHNOLOGY AND APPLICATIONS | 更新时间：2021-05-19

- Control of field flatness based on FPGA for multi-cell cavity
- NUCLEAR TECHNIQUES Vol. 40, Issue 2, Article number: 020101(2017)
- 作者机构：
  
  1.中国科学院上海应用物理研究所嘉定园区上海 201800
  2.上海市低温超导高频腔技术重点实验室上海 201800
- 作者简介：
- 基金信息：
  
  National Natural Science Foundation of China
- DOI：10.11889/j.0253-3219.2017.hjs.40.020101
  CLC： TL506
- Received：05 September 2016，
  
  Revised：18 November 2016，
  
  Published：10 February 2017
- 稿件说明：
移动端阅览
Zhigang ZHANG, Yubin ZHAO, Kai XU, et al. Control of field flatness based on FPGA for multi-cell cavity[J]. Nuclear techniques, 2017, 40(2): 020101
DOI：

Zhigang ZHANG, Yubin ZHAO, Kai XU, et al. Control of field flatness based on FPGA for multi-cell cavity[J]. Nuclear techniques, 2017, 40(2): 020101 DOI： 10.11889/j.0253-3219.2017.hjs.40.020101.

摘要

在多cell腔的场平坦度控制处理中，最重要的算法为除法运算，而传统整数除法算法采用多次相减和移位的方法来实现，其算法存在以下缺点：相减运算消耗大量时钟即“吃时钟”、每完成一次算法所需时钟周期不固定以及此算法在实际工程中不能有效工作。针对传统整数除法器的弊端，提出一种基于现场可编程门阵列（Field-Programmable Gate Array，FPGA）的循环型不可恢复除法器。设计的循环型不可恢复除法器通过改善程序结构和优化时序，实现除法运算速度的提高和固定运算所需时钟周期的目的。此算法通过QuartusII编译和综合，以及仿真工具ModelSim的仿真验证，达到预期功能效果，同时在上海光源增强器高频数字低电平控制器中被采用，实现场平坦度稳定度在±1.3%以内，完成每次运算所需35个时钟周期，优于设计指标。

Abstract

Background:

The most important processing is division in the algorithm for the field flatness controller on multi-cell cavity. The algorithm in conventional integer division uses multiple subtraction and shift methods to achieve the operation. A lot of clocks are consumed in the subtraction process

and the cycles consuming is not fixed on each cycle of the division.

Purpose:

This study aims to design a circular unrecoverable divider based on FPGA (Field-Programmable Gate Array).

Methods:

Improvement is taken for meliorating the program structure and optimizing the time sequences to achieve speedup of the division and same clock cycle for each conventional division. This algorithm is implemented on FPGA chip using QuartusII

simulated and verified by ModelSim toolkits.

Results:

The stability of field flatness is less than ±1.3% and 35 cycles for each algorithm when it applied in the controller of DLLRF (Digital Low Level Radio Frequency) for the booster of Shanghai Synchrotron Radiation Facility (SSRF).

Conclusion:

Control of field flatness based on FPGA for multi-cell cavity satisfies all functional requirements

overperforms the design expectations.

关键词

Keywords

references

Z G Zhang , Y B Zhao , K Xu , . Digital LLRF controller for SSRF booster RF system upgrade . Nuclear Science and Techniques , 2015 . 26 ( 3 ): 030106 DOI: 10.13538/j.1001-8042/nst.26.030106 http://doi.org/10.13538/j.1001-8042/nst.26.030106 .

Hassanzadegan H, Perez F. Analogue LLRF for the ALBA booster[C]. Proceedings of the 11th European Particle Accelerator Conference, Genoa, Italy, 2008: 1416-1418.

M H Jiang , X Yang , H J Xu , . Shanghai synchrotron radiation facility . Chinese Science Bulletin , 2009 . 54 4171 - 4181 . DOI: 10.1007/s11434-009-0689-y http://doi.org/10.1007/s11434-009-0689-y .

Gu Q, Chen L X, Chen M, et al. RF system for the SSRF booster synchrotron[C]. Proceedings of the 11th European Particle Accelerator Conference, Genoa, Italy, 2008: 754-756.

张志刚 , 赵玉彬 , 徐凯 , . 基于I/Q解调原理的校准方法及实验 . 核技术 , 2015 . 38 ( 3 ): 030102 DOI: 10.11889/j.0253-3219.2015.hjs.38.030102 http://doi.org/10.11889/j.0253-3219.2015.hjs.38.030102 http://www.j.sinap.ac.cn/hejishu/CN/abstract/abstract380.shtml .

Zhigang ZHANG , Yubin ZHAO , Kai XU , . Calibration method and experiment based on I/Q demodulation principle . Nuclear Techniques , 2015 . 38 ( 3 ): 030102 DOI: 10.11889/j.0253-3219.2015.hjs.38.030102 http://doi.org/10.11889/j.0253-3219.2015.hjs.38.030102 http://www.j.sinap.ac.cn/hejishu/CN/abstract/abstract380.shtml .

钟少鹏 , 赵明华 , 张俊强 . 数字化I/Q技术用于磁控管频率控制 . 核技术 , 2014 . 37 ( 4 ): 040103 DOI: 10.11889/j.0253-3219.2014.hjs.37.040103 http://doi.org/10.11889/j.0253-3219.2014.hjs.37.040103 http://www.j.sinap.ac.cn/hejishu/CN/abstract/abstract179.shtml .

Shaopeng ZHONG , Minghua ZHAO , Junqiang ZHANG . Digital I/Q technology used for magnetron frequency control . Nuclear Techniques , 2014 . 37 ( 4 ): 040103 DOI: 10.11889/j.0253-3219.2014.hjs.37.040103 http://doi.org/10.11889/j.0253-3219.2014.hjs.37.040103 http://www.j.sinap.ac.cn/hejishu/CN/abstract/abstract179.shtml .

刘波 . 精通Verilog HDL语言编程 , : 北京电子工业出版社 , 2007 . 461 - 464 .

Bo LIU . Proficient in Verilog HDL programming language , : Beijing Electronic Industry Press , 2007 . 461 - 464 .

叶显阳 , 张海勇 , 皮代军 , . 基于Verilog计算精度可调的整数除法器的设计 . 现代电子技术 , 2009 . 32 ( 3 ): 146 - 148 . DOI: 10.3969/j.issn.1004-373x.2009.03.046 http://doi.org/10.3969/j.issn.1004-373x.2009.03.046 .

Xianyang YE , Haiyong ZHANG , Daijun PI , . Design of integer divider with adjustable precision based on Verilog . Modern Electronics Technique , 2009 . 32 ( 3 ): 146 - 148 . DOI: 10.3969/j.issn.1004-373x.2009.03.046 http://doi.org/10.3969/j.issn.1004-373x.2009.03.046 .

周殿凤 , 王俊华 . 基于FPGA的32位除法器设计 . 信息化研究 , 2010 . 36 ( 3 ): 26 - 28 . DOI: 10.3969/j.issn.1674-4888.2010.03.008 http://doi.org/10.3969/j.issn.1674-4888.2010.03.008 .

Dianfeng ZHOU , Junhua WANG . Design of a 32-bit divider based on FPGA . Informatization Research , 2010 . 36 ( 3 ): 26 - 28 . DOI: 10.3969/j.issn.1674-4888.2010.03.008 http://doi.org/10.3969/j.issn.1674-4888.2010.03.008 .

李文彬 , 陈金鹰 , 王惟洁 , . 基于FPGA的32位循环型除法器设计 . 物联网技术 , 2014 . 25 ( 11 ): 62 - 63 . DOI: 10.3969/j.issn.2095-1302.2014.11.025 http://doi.org/10.3969/j.issn.2095-1302.2014.11.025 .

Wenbin LI , Jinying CHEN , Weijie WANG , . Design of a 32-bit circular divider based on FPGA . Internet of Things , 2014 . 25 ( 11 ): 62 - 63 . DOI: 10.3969/j.issn.2095-1302.2014.11.025 http://doi.org/10.3969/j.issn.2095-1302.2014.11.025 .

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