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1. 中国科学院上海应用物理研究所 嘉定园区,上海,201800
2. 中国科学院核辐射与核能技术重点实验室,上海,201800
3. 中国科学院大学,北京,100049
Published:09 April 2015
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LIU Ye, LIU Zhenbao, HOU Jie. Design and implementation of FPGA-based digital and logical signal processing functions of reactor protection system for TMSR[J]. Nuclear techniques, 2015, 38(4): 040404
LIU Ye, LIU Zhenbao, HOU Jie. Design and implementation of FPGA-based digital and logical signal processing functions of reactor protection system for TMSR[J]. Nuclear techniques, 2015, 38(4): 040404 DOI: 10.11889/j.0253-3219.2015.hjs.38.040404.
现场可编程逻辑门阵列(Field Programmable Gate Array
FPGA)在反应堆保护系统中得到越来越广泛的应用。中国科学院上海应用物理研究所的钍基熔盐堆(Thorium Molten Salt Reactor
TMSR)核能系统先导项目拟采用FPGA技术开发数字化的反应堆保护系统,本文探讨使用FPGA设计TMSR保护系统的数字信号处理(模数转换芯片驱动、数字滤波、定值比较)以及逻辑处理(逻辑符合)功能模块,同时通过软件仿真和硬件测试,为FPGA功能验证和确认(V&V)打基础。软件仿真和硬件测试结果表明在TMSR保护系统内使用FPGA实现数字信号处理与逻辑处理在技术上是可行的。
Background: Field Programmable Gate Array (FPGA) can be used to overcome the software common cause failures (CCF)
thus is a more and more widely applied to design the Digital Reactor Protection System (DRPS). There are many companies such as State Nuclear Power Automation System Engineering Company (SNPAS
China)
RPC Radiy (Ukraine)
etc.
are doing research on FPGA-based DRPS. Thorium Molten Salt Reactor (TMSR) project plans to do the same work now. Purpose: Digital signal process (analog to digital converter driven
digital filter
and quantitative comparison)
logic process (two-out-of-four logic
2oo4) and data communication are some key components in DRPS design. It is important to test whether FPGA is able to realize these key techniques or not. Methods: First of all
the flash-based FPGA made by Actel Company is selected to design for digital signal process and logic process
and coded by Verilog Hardware Description Language (Verilog HDL
Verilog) under Libero SoC program. Then the Icarus Verilog (iVerilog) program is employed for simulation
and finally the signal waveform is watched by GtkWave program. Hardware test is performed by using FPGA development board together with some necessary chips. Results: Experimental results showed that the digital signal process and logic process were realized in the dedicated FPGA and performed well. Analog to Digital Converter (ADC) driven module was stable and executed as fast as the ADC chip could. Digital filter module made the ADC data much more stable. Quantitative comparison module got expected results accurately. The 2oo4 logic module gave the result immediately when the inputs had 2 or more “1”. It is of most importance that all of these modules worked simultaneously. Conclusion: It is practicable to use flash-based FPGA in DRPS of TMSR project technically due to its non-software common cause failure
fast speed
simplification and parallelism. Abstract
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