QIAN Yi1 SU Hong1 KONG Jie1, 2 DONG Chengfu1 MA Xiaoli1 LI Xiaogang1 1. Design and implement of a test system for front-end ASIC chips[J]. Nuclear techniques, 2009, 32(9): 701-705.
QIAN Yi1 SU Hong1 KONG Jie1, 2 DONG Chengfu1 MA Xiaoli1 LI Xiaogang1 1. Design and implement of a test system for front-end ASIC chips[J]. Nuclear techniques, 2009, 32(9): 701-705.DOI:
Design and implement of a test system for front-end ASIC chips
A test system for front-end ASIC chip that developed for optimum performance with silicon strip detector was presented in this paper.The main circuit
implementation of a fast read-out control pulse generator based on CPLD and the realization of I2C bus using lines in parallel port were introduced.And the debugging and the performance analysis of the testing system were described.