LIN Feiyu1, 2 QIAO Weimin1 WANG Yanyu1 GUO Yuhui1 1. Development of a synchrotron timing system on a programmable chip[J]. Nuclear techniques, 2009, 32(10): 737-741.
LIN Feiyu1, 2 QIAO Weimin1 WANG Yanyu1 GUO Yuhui1 1. Development of a synchrotron timing system on a programmable chip[J]. Nuclear techniques, 2009, 32(10): 737-741.DOI:
Development of a synchrotron timing system on a programmable chip
A synchrotron requires extremely high time constraints for timing signals
so timing system is very important for a synchrotron control system.A FPGA+ARM+Linux+DSP architecture has been mainly used in timing control of the HIRFL-CSR control system.In this paper
we report the development of the SOPC(System On a Programmable Chip) based on FPGA and uClinux.It can integrate all the functions of ARM+Linux in one single FPGA chip
hence no need of the dedicated ARM chip
and the reduced cost.The maximum operation frequency of this system is 185 MHz.The hardware consumes less than 4% of total resources of FPGA chip.And both the hardware system and the operating system of the SOPC are reconfigurable.The SOPC system has a wide prospect of applications in accelerator engineering and many fields of scientific research.