High precision simple interpolation asynchronous FIFO of HIRFL-CSRe was developed based on the ACEX1K30 FPGA in VHDL Hardware Description language. The FIFO runs in FPGA of DSP module of HIRFL-CSRe. The input data of FIFO is from DSP data bus and the output data is to DAC data bus. It’s kernel adopts double buffer ping-pong mode and it can implement simple interpolation inside FPGA. The module can control out- put data time delay in 40 ns. The experimental results indicate that this module is practical and accurate to HIRFL-CSRe.