An FPGA-based amplitude and phase control of sub-harmonic buncher

ZHANG Junqiang1; 2 YIN Chongxian1 GAO Yongqiang YU Luyang1 ZHAO Minghua1 ZHONG Shaopeng1 1

doi:null

您当前的位置：

首页 >

文章列表页 >

An FPGA-based amplitude and phase control of sub-harmonic buncher

更新时间：2021-03-05

- An FPGA-based amplitude and phase control of sub-harmonic buncher
- NUCLEAR TECHNIQUES Vol. 35, Issue 7, (2012)
- 作者机构：
  
  1. 中国科学院上海应用物理研究所
  2. 中国科学院研究生院
  3. 临沂大学
- 作者简介：
- 基金信息：
- DOI：
  CLC： TN791;TL503
- Published：01 July 2012
- 稿件说明：
移动端阅览
[1]张俊强,殷重先,高永强,俞路阳,赵明华,钟少鹏.FPGA实现次谐波聚束器的幅相控制[J].核技术,2012,35(07):499-502.

ZHANG Junqiang1, 2 YIN Chongxian1 GAO Yongqiang YU Luyang1 ZHAO Minghua1 ZHONG Shaopeng1 1. An FPGA-based amplitude and phase control of sub-harmonic buncher[J]. Nuclear techniques, 2012, 35(7): 499-502.
[1]张俊强,殷重先,高永强,俞路阳,赵明华,钟少鹏.FPGA实现次谐波聚束器的幅相控制[J].核技术,2012,35(07):499-502. DOI：

ZHANG Junqiang1, 2 YIN Chongxian1 GAO Yongqiang YU Luyang1 ZHAO Minghua1 ZHONG Shaopeng1 1. An FPGA-based amplitude and phase control of sub-harmonic buncher[J]. Nuclear techniques, 2012, 35(7): 499-502. DOI：

摘要

为满足上海光源Top-up运行模式的需要

保证光源直线加速器提供稳定的、高品质的束流

研制了次谐波聚束器的低电平控制系统。以可编程逻辑门阵列（FPGA）为基础

利用上下变频、IQ调制解调技术实现了次谐波聚束器幅度和相位的反馈控制。介绍了数字化技术的原理及上层应用程序的开发

并进行桌面测试

实现了幅度控制精度1%、相位控制精度1的技术指标。

Abstract

To satisfy the Top-up operation mode of Shanghai Synchrotron Radiation Facility(SSRF)

and ensure the linac to provide stable and high current beam bunches

a low level radio frequency(LLRF) control system was developed for sub-harmonic buncher.Based on field programmable gate array(FPGA)

LLRF realized digital amplitude and phase feedback control by using up-down converter

IQ modulator and demodulator techniques.Digital principles and application programs were introduced

and table test was performed.The LLRF system achieved an amplitude control accuracy rate of 1 % and phase control accuracy of 1

well meeting the design requirement.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design and development of SHINE accelerator fast interlock system

Research on synchronous radiation scanning transmission X-ray microscopy system closed-loop control method

Performance test of front-end ASIC chip CSNS_VASD developed for China Spallation Neutron Source

Development of on-the-fly mode control system for Hefei Light Source

Design and implementation of network topology for HEPS fast orbit feedback system

Related Author

YU Chunlei

CHEN Guanghua

DING Jianguo

LI Ming

XIAO Qingwen

YAN Yingbing

YAO Zhen

JIAO Yuchen

Related Institution

Shanghai Advanced Research Institute, Chinese Academy of Sciences

Shanghai Institute for Advanced Study, Chinese Academy of Sciences

ShanghaiTech University

Shanghai Institute of Applied Physics, Chinese Academy of Sciences

The University of Texas at Austin

AI问答

Address：2019 Jialuo Road, Jiading, Shanghai, China Postal code：201800
Tel：021-39194977 Email：LHB@sinap.ac.cn
Technical support is provided by Beijing Founder electronics co., LTD 沪ICP备05005479号-1 京公网安备11010802024621
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.
Total Visits：881214 Visits Today：741

⁰